The present invention generally relates to forward error correction (FEC) and, more specifically, to a method and system for providing high-speed, multi-channel FEC using external SDRAM.
Convolutional interleavers and deinterleavers are commonly employed in an FEC scheme to protect against a burst of errors from being sent to a block decoder, such as a Reed-Solomon decoder. It is well known that interleaving techniques improve error correction capability.
FIG. 1 is a simplified schematic block diagram illustrating a typical convolutional interleaver and deinterleaver. In many applications, interleaved data are buffered using static random access memory (SRAM). The width of data to be stored into the memory matches the interleaver/deinterleaver symbol size. For the interleaver 10, each successive branch (102, 103, . . . , 109) has J more symbols than the immediately preceding branch. For example, branch 103 has J more symbols than branch 102. To the contrary, for the deinterleaver 20, each successive branch (102′, 103′, 104′, . . . , 109′) has J fewer symbols than the immediately preceding branch. For example, branch 103′ has J fewer symbols than branch 102′. Unless indicated otherwise, “I” represents the interleaving depth and “J” represents the interleaving increment. Thus, one branch has a different delay from another branch. The foregoing characteristic, i.e., the delay difference, thus creates sequential-write addresses and non-sequential-read addresses, or vice versa, when conventional memory access is used. This asymmetry between write and read addresses affects data throughput. Furthermore, another problem associated with SRAM is that SRAM is relatively more expensive than other types of memory, such as, synchronous dynamic random access memory (SDRAM).
In some applications, SDRAM is used to store interleaved data. However, use of SDRAM based on the interleaving/deinterleaving approach described above also has its disadvantages. For example, one disadvantage is that by using conventional SDRAM access, the overhead ACTIVE and PRECHARGE command cycles for non-sequential read or write addresses significantly reduce data throughput. Another disadvantage is that when conventional SDRAM is used, some applications may not have enough bandwidth to satisfy the requirement that the data width associated with the memory needs to be equal to the symbol size.
Hence, it would be desirable to provide a method and system that is able to handle interleaving and deinterleaving in a more efficient manner.